[10000印刷√] Verilog Ifdef Example 150005-Verilog Define Example
Preprocessorifdefminutia Subtle notes about or `define and `ifdef handling There are many subtleties related to `define and `ifdef that make my head hurt BOZO most of my testing was done on VerilogXL before I really knew much about NCVerilog It would be good to doublecheck all of these things on NCVerilog and make sure it behaves the same